A phase-locked loop, or “PLL,” is a closed loop frequency control system that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. Typically, a PLL is used to generate a higher frequency clock that is used by a chip or digital device to perform computations or other operations.
FIG. 1 illustrates an example chip device 10 that includes, among other things, a digital block 12, a PLL 14, and a regulator 16. Digital block 12 may be any chip, set of chips, or other digital device operable to perform computations or other digital operations. PLL 14 generates clock signals 18 that are used to drive the computations or other operations performed by digital block 12. Regulator 16 serves multiple purposes. First, regulator 16 supplies an input current, IPLL, to PLL 14 in order to drive PLL 14. Second, regulator 16 regulates the output voltage supplied to PLL 14, which may be referred to as VOUT. Regulator 16 receives a high-voltage analog input voltage, VDDAHV, and a reference voltage input, VREF. The input voltage VDDAHV may be received from outside chip device 10, and is higher than the voltage output by regulator 16, VOUT. The voltage VREF indicates to the regulator the desired output voltage, VOUT. The output voltage of regulator 16, VOUT, is thus ideally equal to, or approximately equal to, the reference voltage input, VREF. Regulator 16 attempts to minimize variations in VOUT that may be caused by variations in VDDAHV. In particular, regulator 16 attempts to minimize the power supply rejection ratio (PSRR), which is equal to the variation of VOUT divided by the variation of VDDAHV, as shown below.                     PSRR        =                              variation            ⁢                                                  ⁢            of            ⁢                                                  ⁢                          V              OUT                                            variation            ⁢                                                  ⁢            of            ⁢                                                  ⁢                          V              DDAHV                                                          (        1        )            In addition, regulator 16 attempts to hold VOUT constant over the range of the level of current, IPLL, required by PLL 14 to operate over the specified frequency range under all possible conditions such as temperature ranges and processing variables.
FIG. 2 illustrates a typical circuit topography of regulator 16, which is referred to herein as a “enhanced source follower” topography. Regulator 16 includes a negative feedback loop, indicated at 30, that includes a high-gain operational amplifier (or “op-amp”), transistors 32 and 34, and an active load I2. This negative feedback arrangement is well known to produce an output voltage, VOUT, that closely approximates the reference input voltage, VREF. Regulator 16 includes two current sources, I1 and I2, both of which are constant. ILOAD represents the current drawn by a load, such as PLL 14, for example (as discussed above with regard to FIG. 1).
This topography has a lower output impedance than a simple source follower using only a single transistor 32 and current source I1. This is due to the additional negative feedback through the transistor 34 coupled with the fact that the bias current of transistor 32 is kept constant at I2. Applying Kirchoff's law to the topography of regulator 16 yields:I1=I2+I3+ILOAD  (2)Since I1 and I2 are constant, an increase in ILOAD (current demand) is reflected as a corresponding decrease in I3, and vice versa.
In addition, from Equation (2) it can be seen that all of the current being drawn by PLL 14, namely ILOAD, must come from the source current I1. I1 is therefore established as a fixed current sufficient to supply the maximum anticipated load current, ILOAD (i.e., the maximum anticipated current required by PLL, IPLL), in addition to fixed current I2.
With the arrangement shown in FIG. 2, the fixed supply current I1 is drawn from the supply VDDAHV regardless of variations in the load current ILOAD. Thus, when ILOAD is less than the maximum anticipated value for ILOAD, I1 is drawing more current than is required. This extra current is dissipated by regulator 16 (largely by the not-illustrated transistor(s) needed to provide I1), which is inefficient and generates undesired heat. It would therefore be desirable to have the source current of regulator 16 variable with the load current, ILOAD in order to conserve current and reduce power dissipation when the required ILOAD is lower than the maximum value, such as when PLL 14 operates at relatively low frequencies, for example.